Semiconductor Export Controls: China’s Workaround Architectures

The Chiplet Strategy

The most technically sophisticated of China’s workaround approaches is the adoption of chiplet-based architectures that combine multiple smaller dies into a single package, achieving aggregate compute performance that approaches — though does not match — monolithic designs manufactured at leading-edge nodes.

Huawei’s Ascend 920, released in late 2025, is the most visible example. The chip uses a multi-die architecture with four 7nm compute chiplets interconnected via a domestically produced advanced packaging substrate. Each individual chiplet falls below the performance thresholds specified in the October 2023 export control rules, but the aggregate package delivers AI training performance roughly equivalent to an NVIDIA A100 — a chip that was itself restricted under the earlier October 2022 controls.

The chiplet approach has clear limitations. Inter-die communication latency and bandwidth constraints mean that chiplet-based designs are inherently less efficient than monolithic alternatives for memory-bandwidth-intensive workloads. Current Chinese chiplet interconnect technology delivers approximately 60–70% of the per-watt efficiency of equivalent TSMC CoWoS packaging used in NVIDIA’s Blackwell architecture. For large-scale AI training, this efficiency gap compounds across thousands of chips, translating to significantly higher power consumption and infrastructure costs.

Domestic EDA Development

Electronic design automation (EDA) tools — the software used to design semiconductor chips — represent perhaps the most underappreciated chokepoint in the semiconductor supply chain. Three US-headquartered companies (Synopsys, Cadence, and Siemens EDA) control over 85% of the global EDA market. US export controls restrict the sale of advanced EDA tools to Chinese chip designers, forcing reliance on domestic alternatives.

Chinese EDA development has accelerated significantly since 2022:

• Empyrean Technology (formerly Huada Jiutian) has released a full-flow EDA suite capable of supporting designs at the 14nm node, with 7nm support in advanced beta testing. The tool chain covers logic synthesis, physical design, verification, and sign-off — the complete design flow.
• X-EPIC has developed analogue and mixed-signal EDA tools that are in production use at several Chinese semiconductor design houses for mature-node chips.
• Government funding: The National Integrated Circuit Industry Investment Fund (“Big Fund”) Phase III, capitalised at approximately $47 billion, has allocated an estimated 15% to EDA and design tool development — a significant increase from Phase II allocations.

The gap remains substantial. Chinese EDA tools are functional for mature-node design but lack the accuracy and optimisation capability required for leading-edge processes (5nm and below). Chip designs produced with current Chinese EDA tools exhibit higher defect rates and lower yield optimisation compared to equivalent designs using Synopsys or Cadence tool chains. This is a problem that improves incrementally with investment and iteration, but closing the gap to parity is likely a 5–8 year trajectory.

Third-Country Procurement

The most difficult workaround to counter is the use of third-country intermediaries to acquire controlled technology. US Bureau of Industry and Security (BIS) enforcement actions in 2025 identified procurement networks operating through Malaysia, Singapore, the UAE, and Central Asian states that were sourcing controlled chips and semiconductor manufacturing equipment for end users in China.

The scale of this activity is difficult to quantify precisely, but trade data provides indicative signals:

• Malaysia’s semiconductor equipment imports from the Netherlands (home to ASML) increased by 340% between 2022 and 2025, a volume that substantially exceeds Malaysia’s domestic fabrication capacity requirements.
• Singapore-based trading companies have been identified as intermediaries in at least 14 BIS enforcement cases involving controlled NVIDIA chips destined for Chinese data centres.
• UAE free trade zones have emerged as a significant transit point, with several entities placed on the BIS Entity List in January 2026 for facilitating controlled technology transfers.

The US response has been to expand the Entity List aggressively and to pressure allied governments to implement parallel export control regimes. The Netherlands and Japan have both enacted restrictions on semiconductor manufacturing equipment exports, though enforcement varies. The fundamental challenge is that export controls are a leaky instrument — they can slow and increase the cost of technology acquisition, but they cannot prevent it entirely when the economic incentives for circumvention are sufficiently large.

SMIC and the Lithography Question

Semiconductor Manufacturing International Corporation (SMIC), China’s most advanced foundry, continues to produce chips at the 7nm node using older DUV (deep ultraviolet) lithography equipment acquired before the most restrictive export controls took effect. SMIC has reportedly achieved yields of 70–75% on its N+2 process (equivalent to 7nm) — commercially viable, though well below TSMC’s 90%+ yields at the same node.

The critical constraint is EUV (extreme ultraviolet) lithography. ASML remains the sole global supplier of EUV systems, and Dutch export controls effectively prevent any delivery to China. Without EUV, SMIC cannot economically manufacture chips below the 7nm node. Chinese efforts to develop domestic EUV capability are underway at the Chinese Academy of Sciences, but credible assessments place a production-ready Chinese EUV system at 2030 at the earliest, with most analysts considering 2032–2035 more realistic.

Implications

For export control policy: The controls are working in the sense that they are imposing a meaningful technology gap and increasing costs. They are not working in the sense of permanently denying China access to AI-relevant compute. The appropriate framing is delay and cost imposition, not denial. Policy should be calibrated accordingly — expectations of hermetic containment are unrealistic.

For the AI compute landscape: China will continue to field AI training infrastructure that is 1.5–2 generations behind the US frontier, with higher energy costs and lower efficiency. This gap is strategically significant for the most compute-intensive frontier model training, but less relevant for inference deployment and fine-tuning of existing architectures. Chinese AI capabilities in application domains (computer vision, natural language processing, autonomous systems) will remain competitive despite the hardware gap.

For semiconductor markets: The export controls are accelerating China’s domestic semiconductor ecosystem development across the full stack. This is an intended consequence of Chinese industrial policy, but the controls are compressing timelines. Within a decade, China will likely have a largely self-sufficient semiconductor ecosystem for mature nodes (28nm and above), reducing the long-term market addressable by US, European, and allied semiconductor firms.

This briefing draws on BIS regulatory filings, semiconductor industry reporting from TrendForce, IC Insights, and SemiAnalysis, academic publications from Chinese research institutions, and open-source trade data. All assessments reflect the analytical judgement of Varangian // Intel and do not represent the position of any government or organisation cited.